Next generation consumer electronics calls for low cost, high performance information displays with high pixel count (resolution) and high response speed. To drive such displays, the thin film transistors (TFT) used for the pixel drivers need sufficient mobility and stability at operating conditions: with Vds typically in 0˜10 v for either LCD or OLED displays. OLED displays and peripheral drivers on panel set up more rigorous requirement on TFT operation lifetime. Amorphous silicon (a-Si) based TFT cannot meet such needs due to low carrier mobility and performance instability. Low temperature polysilicon (LTPS) based TFTs cannot meet such needs due to high unit area cost and uniformity problems over large display area. High mobility metal-oxide TFTs become an attractive candidate due to their LTPS-like performance, and a-Si-like cost and uniformity. From a practical point of view, a MOTFT with a process adaptable to existing display manufacturing lines originally designed for a-Si TFT is more attractive for its short time to market and over capacity business environment.
Three types of TFTs have been used in a-Si based TFTs and MOTFTs. Two types are illustrated in FIGS. 1A and 1B, which show simplified cross-sectional views each with an etch-stop (ES) layer. The type illustrated in FIG. 1A is commonly referred to as the “island ES-type”, the type illustrated in FIG. 1B is commonly referred to as the “via ES-type”, and the type illustrated in FIG. 1C is commonly referred to as the “back-channel-etching (BCE) type” TFT. In the ES type TFTs, the channel length is defined by the length of the dielectric ES between the source and drain electrodes. In the BCE type TFT, the channel length is defined by the gap between the source and drain electrodes.
The ES-type TFTs have the advantage of better protecting the channel during S/D processing. However, the ES-type TFTs have a few disadvantages: (1) they require an extra mask step to pattern the etch-stop layer; and (2) due to the alignment requirements, the minimum channel length is constrained to more than (Lmin+2Lalign+2Ltol), where Lmin is the minimum gap space (often called design rule) for the metal source-drain layer, Lalign is the alignment accuracy, and Ltol is the tolerance for overlap between the S/D metal and the etch-stop. In applications with small pixel pitch, the BCE type TFT is favorable for small TFT dimensions achievable with a given design rule. However, BCE process may damage the top of channel which is more challenge in term of process control. This is especially true for a metal-oxide based channel compared to a silicon based channel.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved process for fabricating a stable, high mobility metal oxide thin film transistor (MOTFT).
It is another object of the present invention to provide a new and improved fabrication process with for producing MOTFTs with fewer process steps.
It is another object of the present invention to provide a new and improved fabrication process for MOTFTs that reduces the minimum channel length.
It is another object of the present invention to provide new and improved stable, high mobility metal oxide thin film transistors (MOTFT).
It is another object of the present invention to provide a low mobility metal-oxide with energy gap between 3 and 4.5 eV as the etch stop layer in MOTFT which provides sufficient electric conduction in vertical direction between S/D electrode and the channel, and provide sufficient insulation in horizontal direction.
It is another object of the present invention to provide a new and improved fabrication process for MOTFTs that includes a blanket thin film etch-stop layer on top of the channel and display pixel area with via holes for S/D contacts and electrode contact.